1. Technical Field
This disclosure relates to semiconductor fabrication, and more particularly, to methods for adjusting etch selectivity between crystallographic planes or directions in silicon.
2. Description of the Related Art
The extendability of deep trench based memory devices is limited by the storage capacitance of the deep trench as the ground rules shrink. Since the capacitance that can be stored in the deep trench is a linear function of the surface area of the deep trench, the formation of a larger trench is beneficial. However, widening a deep trench has a large impact on layout area of a semiconductor chip.
Attempts have been made to increase the surface area of a deep trench below an insulating collar, which is formed within the deep trench. The region below the insulating collar is not as limited in available area as an upper portion of the deep trench. To expand the region below the collar, an isotropic silicon reactive ion etch (RIE) process can be employed. The RIE process recesses a silicon substrate below the insulating collar to provide increased surface area. The RIE process suffers from many disadvantages. These disadvantages include:
1. Low selectivity to oxide. With the reactive ion etch process the insulating collar is also etched thereby reducing the thickness of the insulating collar. The insulating collar is, for example, a LOCOS oxide or a deposited oxide. When this oxide is thinned vertical leakage currents may occur.
2. Expensive process. The RIE tools are expensive and have a low throughput due to the need for single wafer processing.
3. Collateral damage. The RIE process leaves polymer deposits in etched areas which may have a detrimental effect on component performance. The RIE process may cause surface damage to etched areas and undesirable side pockets may be formed in etched areas.
As a result, alternate etching techniques have been employed. These etching techniques attempt to etch bottle shaped trenches by etching a silicon substrate selective to the collar oxide. These etching techniques often provide etching rates, which etch one crystallographic plane of a silicon substrate faster than another crystallographic plane. In a semiconductor memory fabrication process, this may lead to asymmetric shaped bottle-shaped portions of deep trenches. As dimensions for semiconductor devices shrink, any asymmetries may cause overlap between trenches or force a semiconductor device layout to increase in area to accommodate the need for spacings between trenches.
Therefore, a need exists for an improved method for increasing surface area of deep trench capacitors. A further need exists for a method, which symmetrically forms bottle-shaped trench portions to increase the surface area of deep trench capacitors without causing overlap between adjacent trenches and without the disadvantages of reactive ion etching.
Methods for expanding trenches are disclosed. A trench is formed in a substrate having side walls including at least two crystallographic planes. One crystallographic plane is etchable at a faster rate than a second crystallographic plane. A dielectric layer is selectively grown on surfaces of the crystallographic planes such that the dielectric layer includes a greater thickness on one of the crystallographic plane than on the other. The dielectric layer and the substrate are etched such that an etch rate inversion is achieved. That is, the second crystallographic plane is effectively etched at a faster rate than the first crystallographic plane.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.